To aid debug procedures, many processors incorporate a mode in which trace information is recorded so that an executed instruction history may be reconstructed for a particular time segment. The trace information typically represents a history of the value of the instruction pointer as it changes over the time segment and usually is provided as a stream of instruction pointer values. A debug module or diagnostic software then may use this stream of instruction pointer values to identify the corresponding instruction code and thereby determine whether the processor is operating correctly.
In many such processing systems, virtual memory with paging is utilized whereby the instruction pointer is a linear address that may map to a plurality of different physical addresses, where the proper physical address associated with the linear address depends on context. In such instances, the proper association of the recorded stream of instruction pointers to the corresponding instruction code depends on the context of each instruction, where the context defines the mapping of linear addresses to the corresponding physical addresses and typically includes an indication of the processor mode, the values of one or more control registers and the state of the page tables for each instruction executed. However, due to current processor speeds, the context information for each executed instruction typically is too large to be recorded in the trace information or monitored by the processor or an instruction-by-instruction basis. Conventional debug implementations typically assume that the mapping at the termination of the trace applies to the whole trace and thereby disassembles the trace based only on the last context. Consequently, the instructions subsequent to the last context change typically are correctly identified, but those instructions prior to the last context change typically are incorrectly identified, thereby limiting the usefulness of the trace as a debug tool. Accordingly, an improved technique for providing trace information in processors utilizing paging would be advantageous.
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